In testing semiconductor devices by a semiconductor test system, a test pattern must be produced for every new device under test (hereafter "DUT") to be supplied to the DUT. To produce a test pattern through a program, it is required a large amount of time and labor. In semiconductor devices having modern integrated circuit technologies, it has become common to include two or more function blocks or modules in a chip of the device such as an ASIC (Application Specific Integrated Circuit) device. For example, like a DUT 90 or a DUT 91 in FIG. 5, a semiconductor device includes a combination of modules 100 which are various types of function circuits.
Such modules and input/output terminals of the DUT are either directly connected without intervening circuits or indirectly connected through intermediate circuits. In an example of FIG. 6, a function module 100 in the DUT 90 is indirectly connected to the input/output terminals through an intermediate circuit 30. Examples of such intermediate circuits include a parallel-serial conversion circuit, a flip-flop circuit for clock synchronization, a level sensitive scan design (LSSD) circuit and a specific circuit controlled by a processor in the DUT.
In a situation where a function module in a device under test is connected to the input/output pins through an intermediate circuit, the test program formulated for the module can be commonly used even when a difference intermediate circuit is used without modifying the test program. This technology is shown in the Japanese Patent Application Serial No. 7-52432 owned by the same assignee of the present invention and a schematic diagram of which is shown in FIG. 6. The semiconductor test system 10 of FIG. 6 includes a pattern conversion means 20 which inversely converts the test pattern depending on the type of the intermediate circuit 30 in the DUT 90.
In the example of FIG. 6, the pattern conversion means 20 is provided between a pattern generator 11 and a wave formatter 12 and logic comparator 13. The pattern conversion means 20 includes, for example, conversion blocks 20A and 20B corresponding to the kinds of intermediate circuits in the device under test. Switches 21A and 21B are provided so that each of the conversion blocks is switchably inserted in the test system 10.
When the intermediate circuit is not included in the DUT 90, the test patterns from the pattern generator 11 are provided to the DUT 90 without being converted by the conversion means 20. When the intermediate circuit 30 is included in the DUT 90, the corresponding conversion block is selected by the switches 21A and 21B so that the converted test patterns are supplied to the DUT 90 through the wave formatter 12.
In this arrangement, even when a different intermediate circuit 30 is employed in the device under test, the same test pattern as produced for the module 100 can be commonly used for testing the DUT 90 having the module 100. Thus, by having the appropriate conversion blocks in the pattern conversion means 20, the same test pattern can be used even though the DUT includes variety of intermediate circuits so long as the type of the module 100 is identical.
However, some semiconductor devices such as an ASIC has a variety of combination of modules such as DUT 91-93 or DUT 94-96 shown in FIG. 8. In the example of FIG. 8A, each of the DUT 91-93 includes a core CPU and an I/O circuit which are identical to ones in the other DUTs. However, as to the memory modules, capacities of the first memory modules in the DUT 91-93 are different from one another, such as 4K byte, 8K byte or 16K byte.
In the example of FIG. 8B, each of the DUT 94-96 includes the core CPU and the I/O circuit which are the same with each other among the DUTs as in the example of FIG. 8A. As to the memory modules, in the DUT 94-96, although the capacities of the first memory modules are the same, i.e., 4K byte, the memory capacities of the second memory modules are different from one another, such as 128K byte, 256K byte or 512K byte.
Generally, In testing a memory, the different capacity of the memory requires a different test pattern because, for example, address sequence and pattern algorithm must match with the capacity of the memory. Therefore, to test the semiconductor devices having the variety of combination of the modules such as shown in FIG. 8, a large number of different test patterns must be prepared.
FIG. 7 shows an example of test pattern for testing a semiconductor device having modules common to the modules in the other semiconductor devices and other modules different from the modules in the other devices. In this example, the test pattern is formed of a test pattern block 200 and test pattern blocks 250. The test pattern block 200 is for the modules which are common among the devices to be tested and the test blocks 250 are for the modules which are different from device to device.
In testing the DUTs shown in FIG. 8, the test pattern is generated by reading the contents of the test pattern block 200 to test the common modules in the DUTs. At some point of the test pattern, a command signal "CALL" is read from the memory in the pattern generator so that the test pattern is generated by reading the contents of one of the test pattern blocks 250, such as a block 250a to test the module one type of memory module.
Since the test patterns 250a, 250b, . . . 250n are dependent upon the type of modules included in the DUTs, many test patterns must be prepared for testing the DUT having various types of modules. In other words, each test pattern must include the test pattern block 200 for testing the common modules in the DUT and the test pattern blocks 250 for testing the specific modules in the DUT.
As in the foregoing, for testing semiconductor devices having variety of combinations of function modules therein, a large number of test pattern must be prepared corresponding to the combinations. For example, in FIGS. 7 and 8, one test pattern must have test blocks 200 and 250a, and another test pattern must have test blocks 200, 250a and 250b and 250n, and another test pattern must have test blocks 200, 250b and 250n, and so on. Therefore, to produce such a large number of test patterns requires a large amount of time and labor. Since the number of test programs is large, it is also necessary to suitably manage and stock the test programs, which also requires cost and human resources.